1. Field of the Invention
The present invention relates to an array substrate, and more particularly, to an array substrate with asymmetric thin film transistor design and reduced pixel size.
2. Description of the Prior Art
The array substrate (also referred to as thin film transistor substrate) of a display panel includes a plurality of gate lines and data lines, wherein the pixel array are defined by the crossing structure of the gate lines and the data lines, and the pixel array includes a plurality of sub-pixels arranged in an array. As the market demand has changed, high resolution has become one of the most important requirements for display panels. For instance, smart phones with FHD resolution (1920*1080) display panels have been commercialized in the market recently. However, due to the limit of the manufacturing ability, the sizes of the sub-pixels are not able to be further reduced, which becomes the bottleneck for developing high resolution display panels.